Get those clock domains in sync - EDN
File:Metastability D-Flipflops-ru.svg - Wikimedia Commons
Metastability
FPGA-FAQ 0017 Tell me about Metastability
Avoid setup- or hold-time violations during clock domain crossing - EDN Asia
VLSI UNIVERSE: Synchronizers
After metastability, does the value eventually settle to the correct value? - Electrical Engineering Stack Exchange
flipflop - If a flip flop has a setup violation and goes metastable, is it guaranteed to settle to the input value when it finishes oscillating? - Electrical Engineering Stack Exchange
flipflop - What will the output of filp-flop if its input is metastable? - Electrical Engineering Stack Exchange
Experimenting with Metastability and Multiple Clocks on FPGAs – Colin O'Flynn
fpga - How does 2-ff synchronizer ensure proper synchonization? - Electrical Engineering Stack Exchange
Figure 2 from A metastability immune timing error masking flip-flop for dynamic variation tolerance | Semantic Scholar
Metastability immune and area efficient error masking flip-flop for timing error resilient designs - ScienceDirect
What is Metastability in Digital Circuits ? - Technology@Tdzire
Metastability (electronics) - Wikipedia
File:2FF synchronizer.gif - Wikimedia Commons
Metastability (electronics) - Wikipedia
Metastability (electronics) - Wikipedia
Metastability in an FPGA
TechXclusives - Metastability Delay and Mean Time Between Failure in Virtex-II Pro FFs
What Is Metastability?
EDACafe: Automatic Handling of Register Clock Domain Crossings
